Abstract:Aging is becoming one of the most concerning problems for integrated circuits manufactured under ultra-deep sub-micrometer technology, which seriously influences the life span of a chip due to resulting in circuit failure. The existing techniques can only used to detect circuit faults after faults appear. In this paper, a novel on-line circuit aging detecting sensor is designed and inserted between the outputs of a combinational logic and flip-flops to predict circuit failure before errors occur. A stability checker is presented in the sensor, which can not only detect abnormal time delay of a circuit, but also store the detecting result without using any additional latches to retain the output signal when the checker is active, therefore predicting circuit failure. Simulation is executed for benchmarks circuits under 32nm CMOS technology. Experimental results show that compared with the aging detecting schemes recently proposed in the literature, using our technique, the detecting sensor has much less area overhead with lower power dissipation and time delay.

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	1. A Novel Aging Sensor with Function Reuse for Circuit Failure Prediction
	SHI Dongxia,LIANG Huaguo,HUANG Zhengfeng,LIU Yanbin
	Electrics, Communication and Autocontrol Technology 11 March 2012
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	Abstract:Aging is becoming one of the most concerning problems for integrated circuits manufactured under ultra-deep sub-micrometer technology, which seriously influences the life span of a chip due to resulting in circuit failure. The existing techniques can only used to detect circuit faults after faults appear. In this paper, a novel on-line circuit aging detecting sensor is designed and inserted between the outputs of a combinational logic and flip-flops to predict circuit failure before errors occur. A stability checker is presented in the sensor, which can not only detect abnormal time delay of a circuit, but also store the detecting result without using any additional latches to retain the output signal when the checker is active, therefore predicting circuit failure. Simulation is executed for benchmarks circuits under 32nm CMOS technology. Experimental results show that compared with the aging detecting schemes recently proposed in the literature, using our technique, the detecting sensor has much less area overhead with lower power dissipation and time delay.
	TO cite this article:SHI Dongxia,LIANG Huaguo,HUANG Zhengfeng, et al. A Novel Aging Sensor with Function Reuse for Circuit Failure Prediction[OL].[11 March 2012] http://en.paper.edu.cn/en_releasepaper/content/4471166


	2. A method for the solution of the electrostatic properties of metal-(n)AlGaN-GaN two dimensional electron gas
	ZHANG Jinfeng,HAO Yue
	Electrics, Communication and Autocontrol Technology 17 February 2012
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	Abstract:To help explore the electrostatic properties of AlGaN-GaN two dimensional electron gas (2DEG), we present a simple and efficient method to determine the fermi level EF and solve 2DEG distribution and conduction band edge simultaneously, whose essence is to fix EF by two 2DEG sheet density vs. EF relations respectively deduced from Schrfdinger and Poisson equations. This method is applicable to the situation that depletion approximation holds and background doping charge can be omitted, and the polarization effects of nitrides can be combined.
	TO cite this article:ZHANG Jinfeng,HAO Yue. A method for the solution of the electrostatic properties of metal-(n)AlGaN-GaN two dimensional electron gas[OL].[17 February 2012] http://en.paper.edu.cn/en_releasepaper/content/4466959

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	3. Device Characteristics Research of the Overlap Double Gate MOSFET
	HAN Mingjun,CHI Xiaoli,Xue Feng,KE Daoming
	Electrics, Communication and Autocontrol Technology 15 January 2012
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	Abstract:In this paper an overlap double gate structure MOSFET model is researched and compared with split double gate structures in this paper. This structure is emulated by MEDICI software. The simulation results show that the channel surface electric field of the overlap double gate structure is modulated. The short channel effect and hot carrier injection is reduced. Breakdown voltage is increased; meanwhile, the equivalent gate capacitance is dropped. Transconductance could be regulated by gate voltage. Along with the channel shorten, threshold voltage change rate of overlap double gate is smallest than the others.
	TO cite this article:HAN Mingjun,CHI Xiaoli,Xue Feng, et al. Device Characteristics Research of the Overlap Double Gate MOSFET[OL].[15 January 2012] http://en.paper.edu.cn/en_releasepaper/content/4459579


	4. A PSO Parameter Extraction Method for SOI MOSFETs based on BSIM SOI Model
	Zheng Xue ,Zhang Guohe,Shao Jun,Chen Kebin
	Electrics, Communication and Autocontrol Technology 27 December 2011
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	Abstract:Abstract: A parameter extraction and optimization strategy using PSO (Particle Swarm Optimization) algorithm is presented for SOI (Silicon On Insulator) MOSFETs（Metal-Oxide -Semiconductor Field Effect Transistor） based on the BSIM SOI 3.1 model which is developed by the BSIM group of UC Berkeley. The global optimal strategy and standard PSO algorithm are implemented to fulfill the extraction of direct-current parameters, which are related to gate voltage and drain voltage. The values of the optimal parameters, which are got from multiple experiments, are as follows: inertia factor w=0; learning factor c1=c2=2; the initialization of the particle swarm is a random distribution; the value of swarm scale is 30. The algorithm shows a perfect convergence rate and can be used as a possible global extraction method for MOSFETs devices.
	TO cite this article:Zheng Xue ,Zhang Guohe,Shao Jun, et al. A PSO Parameter Extraction Method for SOI MOSFETs based on BSIM SOI Model[OL].[27 December 2011] http://en.paper.edu.cn/en_releasepaper/content/4456270


	5. High-Order Analytic Approximation for MOSFET Surface Potential with Lateral Channel Field Effect
	CHANG Sheng,HUANG Qijun,WANG Gaofeng,WANG Hao
	Electrics, Communication and Autocontrol Technology 11 October 2011
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	Abstract:Gradual channel approximation of MOSFET is not available if lateral channel field effect is considered, and as the result, the profile of surface potential is also changed. In this paper, a high order analytical calculation of MOSFET surface potential, considering lateral channel field effect, is introduced. By maintaining the high order term of basic surface potential formulation, accuracy can be improved greatly while no obvious addition of calculation time.
	TO cite this article:CHANG Sheng,HUANG Qijun,WANG Gaofeng, et al. High-Order Analytic Approximation for MOSFET Surface Potential with Lateral Channel Field Effect[OL].[11 October 2011] http://en.paper.edu.cn/en_releasepaper/content/4444921


	6. Physical Modeling of On-chip Sub-nH Spiral Inductor
	Yang Kang ,Yan Na
	Electrics, Communication and Autocontrol Technology 22 July 2011
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	Abstract:In this paper, a new physical model for sub-nH spiral inductors in CMOS integrated circuits (IC) design is developed. Based on physical analysis of on-chip inductors' high frequency effects, П topology with RLC elements is adopted to capture the lumped characteristics of on-chip sub-nH spiral inductor. The interconnects between inductors and other devices are incorporated into the proposed model, which simplifies the circuit and layout design. The new model demonstrates a good agreement with measured S-parameter within 40GHz through analytical calculation and data fitting. Finally, the proposed inductor model is employed in a 20-GHz 4.8dB-NF low noise amplifier (LNA) design for accurate circuit simulation.
	TO cite this article:Yang Kang ,Yan Na . Physical Modeling of On-chip Sub-nH Spiral Inductor[OL].[22 July 2011] http://en.paper.edu.cn/en_releasepaper/content/4436244


	7. Simultaneous growth mechanism of ZnO microwires and nanotetrapods by a double-stream CVD
	Ma Jinxue,Zhang Heqiu,Sun Kaitong,Qiu Yu,Hu Lizhong
	Electrics, Communication and Autocontrol Technology 21 February 2011
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	Abstract:As fundamental materials for semiconductor devices, low dimensional structures of ZnO have attracted extensive research interest. Ultralong ZnO microwires (MWs) and ZnO nanotetrapods (NTs) have been synthesized simultaneously in different growth regions via a novel double-stream growth chemical vapor deposition (CVD) method. The morphology of ZnO MWs and NTs was investigated by the scanning electron microscopy (SEM). Ultralong ZnO MWs with a perfect hexagonal morphology were formed on the quartz tube in the upstream growth region, and ZnO NTs were deposited on the substrate in the downstream growth region. The novel CVD method is attributed to the special gas flow and the tem-perature distribution in the small quartz tube (SQT). By using the vapor-solid (VS) growth mode and a backflow growth model, the growth mechanism of such unique double-stream growth phenomenon was discussed.
	TO cite this article:Ma Jinxue,Zhang Heqiu,Sun Kaitong, et al. Simultaneous growth mechanism of ZnO microwires and nanotetrapods by a double-stream CVD[OL].[21 February 2011] http://en.paper.edu.cn/en_releasepaper/content/4411434


	8. A high PSR Bandgap Reference in BCD process
	hanjingyu,Yang Bing
	Electrics, Communication and Autocontrol Technology 22 November 2010
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	Abstract:A bandgap reference, which is based on Brokaw bandgap reference and can supply 4.75 v and 1.186 v, is introduced. The low frequency PSR (power-supply rejection) of the 4.75 v output voltage is -133 dB, and the smallest PSR in the frequency range of 1Hz to 1 GHz occurs at 14 MHz, which is -20 dB. And the temperature coefficient of 4.75 v is 45 ppm/℃ in the temperature range of -50℃ to 150℃.
	TO cite this article:hanjingyu,Yang Bing. A high PSR Bandgap Reference in BCD process[OL].[22 November 2010] http://en.paper.edu.cn/en_releasepaper/content/4392780


	9. Design and Simulation of Novel Millimeter-Wave MEMS Transmission Lines
	Zhou Yalin
	Electrics, Communication and Autocontrol Technology 16 November 2010
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	Abstract:The design and development of novel microelectromechanical systems' (MEMS) coplanar waveguide (CPW) transmission lines, using microshield and groove, are presented in the paper to operate between 5-60 GHz. The quasi-static capacitances of CPW are calculated using the conformal mapping technique to express the propagation properties, i.e., the characteristic impedance and effective permittivity. Simulation results have shown a considerable loss reduction to levels that compare favorably with the conventional CPW. These transmission lines can be widely used in the development of phase shifters, filters, and antennas, because of their advantages in loss reduction and improvement in the performance.
	TO cite this article:Zhou Yalin. Design and Simulation of Novel Millimeter-Wave MEMS Transmission Lines[OL].[16 November 2010] http://en.paper.edu.cn/en_releasepaper/content/4391948


	10. CMOS IC DESIGN FOR RELIABILITY - A REVIEW
	Kuang Wei
	Electrics, Communication and Autocontrol Technology 20 November 2009
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	Abstract:The negative bias temperature instability (NBTI), gate oxide breakdown (BD), and HCI (hot carrier injection) are the major wear-out effects on the Complementary Metal Oxide Semiconductor (CMOS) integrated circuit reliability as the CMOS device becomes smaller, especially in the nanoscale size. This paper summarizes much of the recently developed research about the CMOS integrated circuit (IC) design for reliability: from physical level to the circuit level. The tools and algorithm for the CMOS IC design for reliability are also summarized in this paper. It surveys the crucial topics of the CMOS IC design for reliability and the technology to improve the circuit robustness to the wear-out effects.
	TO cite this article:Kuang Wei. CMOS IC DESIGN FOR RELIABILITY - A REVIEW[OL].[20 November 2009] http://en.paper.edu.cn/en_releasepaper/content/36894

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