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	1. Influence of neutron irradiation on persistent photonconductivity in GaN
	ZHANG Minglan,Di Zhaoting,YANG Ruixia
	Electrics, Communication and Autocontrol Technology 14 November 2012
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	Abstract:Unintentionally doped GaN films grown by MOCVD were irradiated with neutron at room temperature. In order to investigate the influence of neutron irradiation, persistent photoconductivity (PPC) and low temperature photoluminescence (PL) measurements were carried out. Pronounced PPC is observed, and yellow luminescence (YL) band is not be detected by PL measurement at 5K, suggesting that PPC and YL are not related. Moreover, PPC phenomena has been enhanced by neutron irradiation and quenched by the followed annealing process at 900 C. The possible origin of PPC in GaN is discussed.
	TO cite this article:ZHANG Minglan,Di Zhaoting,YANG Ruixia. Influence of neutron irradiation on persistent photonconductivity in GaN[OL].[14 November 2012] http://en.paper.edu.cn/en_releasepaper/content/4494811


	2. A 3.4dB NF k-band LNA in 65nm CNOS Technology
	Xu Jianfei,Yan Na
	Electrics, Communication and Autocontrol Technology 28 September 2012
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	Abstract:This paper introduces a design method for k-band (18-26.5 GHz) LNA with best noise performance. Then a k-band LNA is designed following the design method in 65-nm CMOS mixed signal process. The LNA has a peak gain of 20.46 dB at 22.45 GHz and a 3 dB bandwidth of 3.8 GHz. The S11 is better than -11 dB and S22 better than -15 dB across the band. The measured smallest noise figure (NF) is 3.4 dB. The whole chip consumes 11mA current under 1.1V supply voltage and occupies an area of 710 μm × 540 μm.
	TO cite this article:Xu Jianfei,Yan Na. A 3.4dB NF k-band LNA in 65nm CNOS Technology[OL].[28 September 2012] http://en.paper.edu.cn/en_releasepaper/content/4489736

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	3. A Low-Sensitivity Negative Resistance Load Fully Differential OTA under Low Voltage 40nm CMOS Logic Process
	Ning Ning,Fan Yang,Sui Zhiling,Luo Rui,Wu Shuangyi
	Electrics, Communication and Autocontrol Technology 16 March 2012
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	Abstract:A low-sensitivity negative resistance load fully differential operational transconductance amplifier （OTA） with low supply voltage is proposed under standard 40nm logic CMOS process. By using optimized low-sensitivity negative resistance load, the gain immunity towards process variation is effectively improved. Simulated with 40nm logic process model and 1.1V power supply, the results show that the OTA obtained a gain enhancement of 23.85dB and the gain variations is greatly limited.
	TO cite this article:Ning Ning,Fan Yang,Sui Zhiling, et al. A Low-Sensitivity Negative Resistance Load Fully Differential OTA under Low Voltage 40nm CMOS Logic Process[OL].[16 March 2012] http://en.paper.edu.cn/en_releasepaper/content/4471927


	4. Efficient Reliability Dispositioning of Gross Fail Area Defects
	Sun Yanlong,Rong Guoguang
	Electrics, Communication and Autocontrol Technology 11 August 2011
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	Abstract:Various issues in semiconductor manufacturing such as equipment malfunction or process marginalities can result in specific spatial failure patterns of devices at wafer Sort, which could lead to yield or reliability issues in assembly test or with the end customer. Due to the variability and complexity of these Gross Fail Area (GFA) defects, it is difficult, and in some cases nearly impossible to automate the containment and dispositioning of wafers without severely affecting factory output. Containment of impacted material using traditional Statistical Bin Limits (SBL) and limited GFA detection screens post Sort, can often put too much material on hold, or worse, allow impacted material to escape the factory. The current dispositioning procedures are mostly manual and tedious, requiring the review by engineers of large quantities of both affected and unaffected material. The manual procedures, prone to user error, may involve risk of RSI (repetitious stress injury) from the large extent of 'click and kill' inking. In this paper we describe a new breakthrough methodology for automating the accurate screening and inking of certain GFA defects. The wafer map of the Sort bin test results is first converted into a pixel image with just the failed bins that constitute the GFA of interest. Image analysis techniques are applied to identify and extract attributes such as location, size, orientation etc. of the clusters of contiguous failed dice. These attributes are used in rules that are implemented in software to test for the existence of the specific failure patterns, resulting in highly accurate screening. Good die, known to have impaired functionality due to their being adjacent to the clusters meeting specific fail criteria, are then inked programmatically, as their location on the wafer and other descriptive information are known. The entire process is automated, requiring no human intervention.
	TO cite this article:Sun Yanlong,Rong Guoguang. Efficient Reliability Dispositioning of Gross Fail Area Defects[OL].[11 August 2011] http://en.paper.edu.cn/en_releasepaper/content/4438057


	5. Evaluation of the Chip-level Thermal Uniformity for Semiconductor Devices
	ZHANG Guangchen,FENG Shiwei,LI Jingwan,LIU Jing,ZHOU Zhou
	Electrics, Communication and Autocontrol Technology 09 June 2011
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	Abstract:In this paper, a method to evaluate the chip-level thermal uniformity of semiconductor devices by electrical transient thermal response testing is proposed. It's found that the degree of the chip's thermal non-uniformity presents a monotonic increasing relationship with the height of the first step of heating response curves. This phenomenon is observed both in a 3-dimensional transient thermal simulation based on the finite element method (FEM) and transient thermal measurements by electrical temperature sensitive parameter (TSP) method. Chip's surface temperature distributions under different current distributions are also measured by infrared image method and the thermal spectrum method is adopted to analyze the temperature non-uniformity quantitatively. The relationship between the degree of temperature non-uniformity and current distribution is consistent with the result of our proposed method.
	TO cite this article:ZHANG Guangchen,FENG Shiwei,LI Jingwan, et al. Evaluation of the Chip-level Thermal Uniformity for Semiconductor Devices[OL].[ 9 June 2011] http://en.paper.edu.cn/en_releasepaper/content/4431958


	6. Gas sensitive properties of polysiloxane material to organophosphate vapor
	Hu Jia ,Du Xiaosong,Wang Zhidong,Jiang Yadong
	Electrics, Communication and Autocontrol Technology 26 January 2011
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	Abstract:Five functionalized polysiloxane polymers containing phenol, 2-fluorided phenol, 3-fluoro phenol, 2,3-difluoro phenol , 3-methyl fluoro phenol, respectively, have been synthesized and estimated for analysis of the influences of those functional groups on the polymers' sensitivity to dimethyl methyl phosphonate(DMMP). The experimental results shows that those fluoro phenols with stronger hydrogen bond acidity, however, provide smaller sensitivity, compared to phenol. Infrared spectroscopic analysis indicates that forming hydrogen bond of fluorine atom and hydroxy is the reason of increasing the sensitivity and that intermolecular hydrogen bond can make a larger decrease of sensitivity than intramolecular one.
	TO cite this article:Hu Jia ,Du Xiaosong,Wang Zhidong, et al. Gas sensitive properties of polysiloxane material to organophosphate vapor[OL].[26 January 2011] http://en.paper.edu.cn/en_releasepaper/content/4408115


	7. Control technology of pore dimension in the photo-electrochemical etching for high aspect ratios macroporous silicon arrays
	Wang Guozheng,Wang Ji,Qin Xulei,Fu Shencheng,Wang Yang,Li Ye,Duanmu Qingduo
	Electrics, Communication and Autocontrol Technology 12 April 2010
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	Abstract:High aspect ratios macroporous silicon arrays (MSA) have received much attention for their potential applications in silicon microchannel plates, MEMS devices, photonic crystals and so on. In order to fabricating perfect high aspect ratios MSA structure, photo-electrochemical (PEC) etching of MSA and the control technology of pore dimension were studied in detail. The current-voltage curve of a polished n-type silicon wafer was presented in aqueous HF using back-side illumination. The critical current density JPS was discussed and the basic condition of etching current density for steady MSA growth was proposed. An indirectly method was presented to measure the relation of JPS at the pore tip and etching time. The pore dimension was controlled by changing the etching current density according to the measuring result of JPS and high aspect ratios MSA growth was realized. MSA with 317 m of depth and 105 of aspect ratios was obtained.
	TO cite this article:Wang Guozheng,Wang Ji,Qin Xulei, et al. Control technology of pore dimension in the photo-electrochemical etching for high aspect ratios macroporous silicon arrays[OL].[12 April 2010] http://en.paper.edu.cn/en_releasepaper/content/41816


	8. Structural and optical properties of Cr-doped semi-insulating GaN epilayers
	Mei Fei ,Wu Kemin,Pan Yang,Han Tao,Liu Chang
	Electrics, Communication and Autocontrol Technology 24 March 2010
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	Abstract:The properties of Cr-doped semi-insulating GaN epilayers grown by rf-plasma-assisted molecular beam epitaxy were studied. The deep acceptor nature of Cr was used to grow semi-insulating GaN epilayers on sapphire substrates for electronic device applications. The room-temperature (RT) sheet resistivity of the epilayers reached 1010 Ω/square. The activation energy of the dark conductivity was about 0.48 eV. Step-graded AlxGa1-xN/GaN (x=0.3-0.2) superlattices (SLs) were designed to filter dislocations. Transmission electron microscopy images showed that the SLs can dramatically reduce the dislocation density. Al0.35Ga0.65N/GaN heterostructure grown on the Cr-doped semi-insulating GaN epilayer exhibited a RT mobility of 960 cm2/Vs and sheet carrier density of 2.1×1013 cm-2.
	TO cite this article:Mei Fei ,Wu Kemin,Pan Yang, et al. Structural and optical properties of Cr-doped semi-insulating GaN epilayers[OL].[24 March 2010] http://en.paper.edu.cn/en_releasepaper/content/41068


	9. Growth and characterization of InN nanocolumns on InGaN buffer layers
	Yang Pan,Ti Wang,Chang Liu
	Electrics, Communication and Autocontrol Technology 19 March 2010
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	Abstract:C-axis-aligned InN nanocolumns arrays were vertically grown, on 3μm GaN substrates with InGaN buffer layers by radio-frequency molecular beam epitaxy. The density of the nanocolumns could be controlled by adjusting the ratio of In and N. X-ray diffraction, transmission electron microscopy, and field-emission scanning electron microscope were used to study the structural properties of the nanocolumns. And the growth mechanism was studied.
	TO cite this article:Yang Pan,Ti Wang,Chang Liu. Growth and characterization of InN nanocolumns on InGaN buffer layers[OL].[19 March 2010] http://en.paper.edu.cn/en_releasepaper/content/40885


	10. P-FMEA improvement of CMP Micro-scratch
	Cao Xiongwei
	Electrics, Communication and Autocontrol Technology 05 January 2010
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	Abstract:Micro-scratch is a major defect for oxide CMP(including STI/ILD/IMD CMP), serious micro-scratch would form W Puddle, which will make metal short and then cause yield loss. So far no robust method can avoid this issue. Based on P-FMEA theory, do improvement at severity, detection and occurrence three aspects: add process time at post WCMP to decrease micro-scratch impact, making a robust monitor control method to robust detect this issue early and study a method to decreasing the occurrence of this issue. By all of the efforts, Micro-scratch issue at CMP process has much improvement.
	TO cite this article:Cao Xiongwei . P-FMEA improvement of CMP Micro-scratch[OL].[ 5 January 2010] http://en.paper.edu.cn/en_releasepaper/content/38474

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