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A Novel Encoding Architecture of QC-LDPC Codes Based on RAMs
Zhang Wenjun ,Chen Liming *
Inst of Coding & Inform Tech Chongqing Univ. of Posts &Telecomm
*Correspondence author
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Funding: none
Opened online: 6 December 2007
Accepted by: none
Citation: Zhang Wenjun ,Chen Liming .A Novel Encoding Architecture of QC-LDPC Codes Based on RAMs[OL]. [ 6 December 2007] http://en.paper.edu.cn/en_releasepaper/content/16757
 
 
In this paper, a method to mend the encoding architecture based on RAMS is presented for systematic-circulant (SC) form QC-LDPC codes. In this advanced architecture of QC-LDPC Codes Encoder, the RAMs are advisably used to store the parity-check bits and the pointers are introduced as the addresses of the RAMs instead of shift registers used for storing the generator of . Thus, the encoding process can be achieved by reading and writing on RAMs and the parity-check bits can be output serially. Because the encoding architecture doesn’t need any shift registers and parallel to serial circuit, hardware resource is saved and the data throughput is increased.
Keywords:QC-LDPC codes，FPGA，encoder
 
 
 

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