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Sponsored by the Center for Science and Technology Development of the Ministry of Education
Supervised by Ministry of Education of the People's Republic of China
Hierarchical approaches are employed in current floorplanning algorithms for scaling to large number modules. With the development of VLSI technology, the thermal problem has been emerged as one of the key issues for IC design. In this paper, we propose a novel power density clustering method to guide the optimization of floorplanning, which aims to efficiently reduce the hotspots while optimizing design metrics such as area and total wirelength.The experimental results with GSRC benchmarks show that the thermal effect is well controlled so that the temperature of ”hot spots” has decreased on the chip. Our algorithm is compared with the state-of-the-art thermal-aware floorplanning algorithm Hotspot Floorplan, it can reduce the max temperature by 3% while saving time by about 300%.