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Sponsored by the Center for Science and Technology Development of the Ministry of Education
Supervised by Ministry of Education of the People's Republic of China
This paper focuses on the low latency and the fully pipelined implementation of image rotation with memory reduction on FPGA's board. The method we used is based on three-pass algorithm and cubic convolution interpolation. The difficulty of the work is the construction of the fully pipeline as it is hard to get the positional relationship of pixels without storing them after shearing. In this article, mechanisms on judging the row offset and column offset is presented to select pixels in the same row or same column for interpolation in template, which solves the bottleneck of pipeline. Finally, the results of rotation, summary of the memory consumption in FPGA, and the comparison with existing method are presented.