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Modeling and Characterization of On-Chip Interconnects
YIN Wenyan *,ZHAO Wensheng
Centre for optical and electromagnetic research, MOI, Zhejiang university, Hangzhou, 310058, China
*Correspondence author
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Funding: This work was supported partially by the National NSFC under Grant 61171037, the Specialized Research Fund for the Doctoral Program of Higher Educ(No.SRFDP) of China under Grant 20100101110065, the National Basic Research Program under Grant 2009CB320204, and State Key Lab of MOI, Zhejiang University of China)
Opened online: 3 January 2014
Accepted by: none
Citation: YIN Wenyan,ZHAO Wensheng.Modeling and Characterization of On-Chip Interconnects[OL]. [ 3 January 2014] http://en.paper.edu.cn/en_releasepaper/content/4577445
 
 
In this article, one distributed circuit model for the on-chip single interconnect will be introduced at first, where all the lumped elements are frequency-independent and can be directly obtained from its geometrical and physical parameters. This ensures proper scalability of the model parameters because no optimization tuning or fitting for them is involved. Some popular and low-cost techniques, such as patterned ground shield (PGS) structures for suppressing the substrate loss of silicon substrate at high frequencies and differential signal transmission are also addressed here. Then, electromagnetic modeling of on-chip coupled (a)symmetrical interconnects will be performed, including all distributed parameters. The average power handling capability (APHC) of on-chip interconnects and even thin-film microstrip lines (TFML) are also addressed here. Finally, the electrothermal analysis of multilevel interconnects under electrostatic discharge (ESD) stress will be reported using the time-domain FEM.
Keywords:Microwave technique, Interconnect; distributed parameter; average power handling capability; time-domain finite element method (TD-FEM); electrothermal response
 
 
 

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