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FFT Parallel processing method based on ASIP
Tian Run 1,Man Yi 2 *
1.School of electronic Engineering, Beijing University of Posts and Telecommunications, Beijing 100089;School of electronic Engineering, Beijing University of Posts and Telecommunications, Beijing 100089
2.
*Correspondence author
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Funding: none
Opened online: 7 March 2023
Accepted by: none
Citation: Tian Run,Man Yi.FFT Parallel processing method based on ASIP[OL]. [ 7 March 2023] http://en.paper.edu.cn/en_releasepaper/content/4759324
 
 
With the research and development of various types of application-specific instruction-set processor (ASIP), the algorithm library based on single-core general processor can not make full use of the structural characteristics and special instruction set of ASIP. In order to improve the computing performance of ASIP, it is usually necessary to design a special algorithm library. Based on a special processor for 5G small base station wireless communication, this paper optimizes the general FFT algorithm. In this paper, data reordering is added to the Cooley-Tukey algorithm to ensure the natural order of input and output data and increase the data-level parallelism in the algorithm. The optimized algorithm is implemented on the simulator of the dedicated processor using the dedicated instruction set. The experimental results show that the proposed method achieves a high speedup in the dedicated processor.
Keywords:ASIP; FFT; Parallel processing method
 
 
 

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