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CMOS IC DESIGN FOR RELIABILITY - A REVIEW
Kuang Wei * #
Department of Electrical Engineering, Univ. of Texas - PA
*Correspondence author
#Submitted by
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Funding: none
Opened online:20 November 2009
Accepted by: none
Citation: Kuang Wei.CMOS IC DESIGN FOR RELIABILITY - A REVIEW[OL]. [20 November 2009] http://en.paper.edu.cn/en_releasepaper/content/36894
 
 
The negative bias temperature instability (NBTI), gate oxide breakdown (BD), and HCI (hot carrier injection) are the major wear-out effects on the Complementary Metal Oxide Semiconductor (CMOS) integrated circuit reliability as the CMOS device becomes smaller, especially in the nanoscale size. This paper summarizes much of the recently developed research about the CMOS integrated circuit (IC) design for reliability: from physical level to the circuit level. The tools and algorithm for the CMOS IC design for reliability are also summarized in this paper. It surveys the crucial topics of the CMOS IC design for reliability and the technology to improve the circuit robustness to the wear-out effects.
Keywords:CMOS IC;reliability;NBTI;TDDB;HCI;simulation;wear-out effects
 
 
 

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