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A Low Complexity and Memory-Efficient Turbo Architecture for LDPC codes
Lei Xiong * #
School of Electronics and Information Engineering,Beijing Jiaotong University
*Correspondence author
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Funding: 高等学校博士学科点专项科研基金（No.20020004022）
Opened online:16 December 2005
Accepted by: none
Citation: Lei Xiong.A Low Complexity and Memory-Efficient Turbo Architecture for LDPC codes[OL]. [16 December 2005] http://en.paper.edu.cn/en_releasepaper/content/4413
 
 
In this paper, a low complexity and memory-efficient concatenated codes called Parallel Interleaved Concatenated Gallager Codes (PICGCs) are presented. PICGCs combine both better BER performance of long codes and lower complexity and less memory required of short codes. We introduce the construction of PICGCs. The decoding algorithm based on sum-product algorithm is proposed. We also analyze the memory saving and derive its upper bound. The Simulation results show PICGCs can reduce complexity and memory required of decoding significantly with little sacrifice in performance.
Keywords:Low-density parity-check (LDPC) codes, Parallel Interleaved Concatenated Gallager Codes (PICGCs), low complexity, memory-efficient
 
 
 

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