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To date, a combined input and crosspoint queued (CICQ) switch has obtained increasing significant attention for its scalability and simple implementation on FPGA. As the promising next generation high speed packet switch, it is able to address the complex scheduling and high memory access speed problems which exist in other types of switches. However, when distributing packet buffers across crosspoints, it becomes difficult to balance the workload of different buffers, resulting in low memory space efficiency. In this article, we propose a new flow control mechanism to enhance the memory space efficiency, and carry out the performance comparison between such optimized CICQ switch and the one without adopting this mechanism |
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Keywords:communication and information system;switch fabric; CICQ, flow control |
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