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| SV+ is an interactive compiler that makes circuit designer do trade-offs between resource consuming and time cost easily, without rewriting the source code. A set of succinct SV+ syntaxes are proposed in this work. They can be used to embed with Verilog to describe the reconfigurable parts of a circuit. Users have opportunity to select optimization options during the compiling process. The compiler generates Verilog RTL codes, depends on these choices. And for different optimization choices, the circuits vary in architectures besides in time and resource. SV+ syntaxes can describe reconfigurable circuit structures in mathematical or functional level, so designers are liberated from putting much effort on concerning about module scheduling and wire connection. Unlike other circuit compilers, for example DFT compiler[13], which work on single kind of algorithm, SV+ syntaxes can be used in a range of Verilog programs as long as there are any reconfigurable components available in the design. |
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| Keywords:SV+ syntax, Verilog, compiler, circuit |
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