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	1. Load-Aware Transmission Mechanism for NVMeoF Storage Networks
	Qiao Xinghan,Xie Xuchao,Xiao Liquan
	Computer Science and Technology 21 October 2021
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	Abstract:NVMe over TCP is a key technology for building large-scale high-performance storage systems.It can realize NVMeoF (NVMe over Fabrics) storage network based on the existing data center network infrastructure and standard TCP/IP software protocol stack. This article designs and implements the Load-Aware NVMeoF message processing mechanism LANoT (Load-Aware NVMe over TCP). Firstly, the interrupt merging technology based on aggregated PDU is used to alleviate the interrupt storm problem and achieve high throughput. Secondly, matching the special message processing mechanism, which can effectively improve its key performance indicators for applications according to the I/O characteristics of different dedicated queues . This paper implements the LANoT prototype system in the Linux kernel. The performance test results show that compared to the NVMe over TCP implementation in the standard Linux kernel, LANoT can reduce CPU resource consumption by more than 50% and increase IOPS by more than twice.
	TO cite this article:Qiao Xinghan,Xie Xuchao,Xiao Liquan. Load-Aware Transmission Mechanism for NVMeoF Storage Networks[OL].[21 October 2021] http://en.paper.edu.cn/en_releasepaper/content/4755658


	2. A Worst-Case Pattern of Task Load Allocation and Execution for Multiprocessor Global Real-Time Scheduling
	Fengxiang Zhang,Alan Burns
	Computer Science and Technology 27 August 2015
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	Abstract:Multiprocessor scheduling is known to be an NP-hard optimization problem, and no worst-case job arrival sequences have been identified for global scheduling real-time systems. In this paper, we present a novel idea to solve the problem of worst-case scenarios in global scheduling, and firstly introduce a hypothetical parallel executing system where any job except the studied one can be executed in parallel on all processors at any instant in time, we prove that such a hypothetical system leads to a worst-case scenario of any studied job's schedulability, therefore, the proposed results can be used for solving schedulability problems of multiprocessor global scheduling.
	TO cite this article:Fengxiang Zhang,Alan Burns. A Worst-Case Pattern of Task Load Allocation and Execution for Multiprocessor Global Real-Time Scheduling[OL].[27 August 2015] http://en.paper.edu.cn/en_releasepaper/content/4653089


	3. Aegis: A Minimal TCB Code Execution Infrastructure on Legacy Systems
	Liu Chen ,Sun Jianhua ,Chen Hao ,Li Haiwei
	Computer Science and Technology 27 April 2010
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	Abstract:In this paper, we propose a chipset based infrastructure on legacy systems, called Aegis, in which security-sensitive code can safely execute in spite of the compromised OS or DMA devices. Using system management mode which provide complete isolation, we reduce the size of TCB only inc luding security-sensitive code and another few hundreds of lines of additional code. We implement Aegis on an Intel Pentium IV processor and demonstrate how to use it to construct Aegis-enabled code with some examples. Finally, we evaluate the performance of our scheme and provide the results of experimental analysis.
	TO cite this article:Liu Chen ,Sun Jianhua ,Chen Hao , et al. Aegis: A Minimal TCB Code Execution Infrastructure on Legacy Systems[OL].[27 April 2010] http://en.paper.edu.cn/en_releasepaper/content/42400


	4. A Software-Controlled Cache Coherence Optimization for Snoopy-based SMP system
	Zhang Youhui,Ziqiang Qian,Weimin Zheng
	Computer Science and Technology 03 January 2009
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	Abstract:Some testing results show that on average 67% of broadcasts for the maintenance of cache coherence in SMP systems are unnecessary. To reduce the unnecessary overhead of snoopy-based embedded SMP systems, this paper proposes a new software/hardware hybrid cache coherence optimization—the programmer can insert special instructions into programs to direct related hardware to enable/disable broadcast operations, so some potential broadcasts for unshared variables are avoided without violating data coherence. We design the mechanism along with a proposed coherence protocol. Moreover, it is simulated on a SMP simulation platform and the results show that the improvement is apparent. Although the insertion is manual, we believe it accords with the existing SMP programming model.
	TO cite this article:Zhang Youhui,Ziqiang Qian,Weimin Zheng. A Software-Controlled Cache Coherence Optimization for Snoopy-based SMP system[OL].[ 3 January 2009] http://en.paper.edu.cn/en_releasepaper/content/27197


	5. Stack for Biochip-Based DNA Computer
	Li Wanggen ,Chen Li
	Computer Science and Technology 25 August 2008
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	Abstract:Data structure plays an important role in conventional computer. The motivation of this paper is to study the data structure in DNA computer, which can help to improve the application capability of DNA computer. We take stack and queue as an example to discuss their design and implementation. Firstly, we propose a model of biochip-based DNA computer which is fit for implementing the two data structures. Their storage structures are also discussed. Then, we propose the nucleotide-encoding for all components of stack in DNA computer. And, all bio-operations over stack are described. Finally, we give an algorithm example for stack in DNA computer to test the feasibility of our method. All the biological technology mentioned in this paper can be practically implemented in the laboratory. Based on this work, other data structures could be further studied and developed.
	TO cite this article:Li Wanggen ,Chen Li . Stack for Biochip-Based DNA Computer[OL].[25 August 2008] http://en.paper.edu.cn/en_releasepaper/content/23523

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