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1. Simulations and Analysis of the Moving Mask UV Lithography for Thick-photoresist | |||
YU Qian,ZHOU Zaifa,ZHANG Heng | |||
Electrics, Communication and Autocontrol Technology 04 November 2013 | |||
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Abstract:A three-dimensional (3D) simulation system is developed for the moving mask UV lithography of thick photoresist. The exposure simulation model is obtained with consideration of the mask moving function, the refraction and energy loss of the UV light at the surface of photoresist, and the reflection at the photoresist/substrate interface. The development model is calculated by the fast marching method. In addition, the energy deposition distributions and the three-dimensional development profiles are presented under different conditions to study the effect of various parameters and to verify the accuracy by experiment. The results will be useful to understand the effects and to control the exposure conditions in the design process of moving mask UV lithography for thick-photoresist in the future. | |||
TO cite this article:YU Qian,ZHOU Zaifa,ZHANG Heng. Simulations and Analysis of the Moving Mask UV Lithography for Thick-photoresist[OL].[ 4 November 2013] http://en.paper.edu.cn/en_releasepaper/content/4562316 |
2. A Bottleneck-based dynamic scheduling algorithm for semiconductor wafer fabrication | |||
Cao Zhengcai,Deng Jijie | |||
Electrics, Communication and Autocontrol Technology 21 February 2013 | |||
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Abstract:Semiconductor wafer fabrication is a very complicated manufacturing system with characteristics such as reentry of lots into machines, alternative machine with unequal capacity and shifting bottlenecks. The optimization and scheduling of semiconductor wafer fabrication has long been a hot research field. Bottleneck is the key factor to the wafer fabrication which has essential influence on the throughput rate, cycle time, time-delivery rate, etc. The scheduling policies on bottleneck machines have significant impact on cost decreasing, achieving throughput target and improving production-resource scheduling and therefore need to be optimized. In this paper, considering the characteristic information concerning bottleneck and whole production line, a rolling horizon bottleneck prediction method is proposed through predict the wait time of the lot in machines and the machine load. Then, based on the above prediction bottleneck, we proposed a novel rolling horizon dynamic bottleneck-based scheduling algorithm. The algorithm analyzes the key factors which influence the bottleneck shifting and the upstream and downstream scheduling policies of bottleneck. Applied to a simulation wafer fabrication, our proposed bottleneck prediction method and bottleneck-based scheduling algorithm improve the cycle time, machine utility apparently compared to other heuristic scheduling method | |||
TO cite this article:Cao Zhengcai,Deng Jijie. A Bottleneck-based dynamic scheduling algorithm for semiconductor wafer fabrication[OL].[21 February 2013] http://en.paper.edu.cn/en_releasepaper/content/4522240 |
3. Efficient Reliability Dispositioning of Gross Fail Area Defects | |||
Sun Yanlong,Rong Guoguang | |||
Electrics, Communication and Autocontrol Technology 11 August 2011 | |||
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Abstract:Various issues in semiconductor manufacturing such as equipment malfunction or process marginalities can result in specific spatial failure patterns of devices at wafer Sort, which could lead to yield or reliability issues in assembly test or with the end customer. Due to the variability and complexity of these Gross Fail Area (GFA) defects, it is difficult, and in some cases nearly impossible to automate the containment and dispositioning of wafers without severely affecting factory output. Containment of impacted material using traditional Statistical Bin Limits (SBL) and limited GFA detection screens post Sort, can often put too much material on hold, or worse, allow impacted material to escape the factory. The current dispositioning procedures are mostly manual and tedious, requiring the review by engineers of large quantities of both affected and unaffected material. The manual procedures, prone to user error, may involve risk of RSI (repetitious stress injury) from the large extent of 'click and kill' inking. In this paper we describe a new breakthrough methodology for automating the accurate screening and inking of certain GFA defects. The wafer map of the Sort bin test results is first converted into a pixel image with just the failed bins that constitute the GFA of interest. Image analysis techniques are applied to identify and extract attributes such as location, size, orientation etc. of the clusters of contiguous failed dice. These attributes are used in rules that are implemented in software to test for the existence of the specific failure patterns, resulting in highly accurate screening. Good die, known to have impaired functionality due to their being adjacent to the clusters meeting specific fail criteria, are then inked programmatically, as their location on the wafer and other descriptive information are known. The entire process is automated, requiring no human intervention. | |||
TO cite this article:Sun Yanlong,Rong Guoguang. Efficient Reliability Dispositioning of Gross Fail Area Defects[OL].[11 August 2011] http://en.paper.edu.cn/en_releasepaper/content/4438057 |
4. Control technology of pore dimension in the photo-electrochemical etching for high aspect ratios macroporous silicon arrays | |||
Wang Guozheng,Wang Ji,Qin Xulei,Fu Shencheng,Wang Yang,Li Ye,Duanmu Qingduo | |||
Electrics, Communication and Autocontrol Technology 12 April 2010 | |||
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Abstract:High aspect ratios macroporous silicon arrays (MSA) have received much attention for their potential applications in silicon microchannel plates, MEMS devices, photonic crystals and so on. In order to fabricating perfect high aspect ratios MSA structure, photo-electrochemical (PEC) etching of MSA and the control technology of pore dimension were studied in detail. The current-voltage curve of a polished n-type silicon wafer was presented in aqueous HF using back-side illumination. The critical current density JPS was discussed and the basic condition of etching current density for steady MSA growth was proposed. An indirectly method was presented to measure the relation of JPS at the pore tip and etching time. The pore dimension was controlled by changing the etching current density according to the measuring result of JPS and high aspect ratios MSA growth was realized. MSA with 317 m of depth and 105 of aspect ratios was obtained. | |||
TO cite this article:Wang Guozheng,Wang Ji,Qin Xulei, et al. Control technology of pore dimension in the photo-electrochemical etching for high aspect ratios macroporous silicon arrays[OL].[12 April 2010] http://en.paper.edu.cn/en_releasepaper/content/41816 |
5. Control Action of Temperature on ULSI Silicon Substrate CMP Removal Rate and Kinetics Process | |||
Yuling Liu,Xinhuan Niu,Tan Baimei,Wang Shengli | |||
Electrics, Communication and Autocontrol Technology 07 January 2009 | |||
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Abstract:The kinetics process and control process of chemical mechanical high precision finishing for material surface were studied in this paper. According to the experiments, the seven kinetics process for chemical mechanical polishing(CMP) was generalized. Through investigating the CMP process of ULSI silicon substrate, we found that chemical process was the CMP control process under the same mechanical action condition, which was caused by temperature. Such key factor of influencing chemical reactions was effectively settled, which was advantageous to improving other materials CMP removal rate. | |||
TO cite this article:Yuling Liu,Xinhuan Niu,Tan Baimei, et al. Control Action of Temperature on ULSI Silicon Substrate CMP Removal Rate and Kinetics Process[OL].[ 7 January 2009] http://en.paper.edu.cn/en_releasepaper/content/27423 |
6. Control technique of Sapphire roughness in CMP processing | |||
Yuling Liu,Baimei Tan,Niu Xinhuan,Zhao Haitao | |||
Electrics, Communication and Autocontrol Technology 06 January 2009 | |||
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Abstract:Sapphire is the main substrate for the third generation semiconductor materials-GaN. The surface quality directly affects device performance. In this paper, chemical mechanical polishing (CMP) of sapphire substrate is studied, several factors which influence the CMP quality are analyzed, and the mechanism of CMP model is discussed. Small size (20~30nm) and low dispersion silica sol is used as abrasive, which can avoid scratches caused by abrasive granules with uneven diameter. The complex surfactant of the slurry can reduce the surface tension and accelerate the mass transfer of the reactant and reaction product effectively, which can accelerate the reaction and lead to better concave-convex selectivity and low roughness. We also find that the mass transfer is related with the temperature, the higher the temperature, the faster the transmission speed. So the removal rate is higher. By controlling the polishing temperature, the roughness can reach 0.2nm and the perfect sapphire surface is achieved. | |||
TO cite this article:Yuling Liu,Baimei Tan,Niu Xinhuan, et al. Control technique of Sapphire roughness in CMP processing[OL].[ 6 January 2009] http://en.paper.edu.cn/en_releasepaper/content/27391 |
7. Atomistic Simulation on Ion Implantation and Annealing | |||
Min Yu,Ru Huang,Xing Zhang | |||
Electrics, Communication and Autocontrol Technology 12 December 2005 | |||
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Abstract:A reliable and efficient molecular dynamics program to simulate the low energy ion implantation is developed. The newest physical models are included and some efficient algorithms are used to conduct realistic and accurate simulations. By comparing the simulation results with the SIMS data for B, As and P, the program is verified. An atomistic model for annealing simulation is presented. The simulation is carried out for RTA annealing after B implantation. Agreements between simulation and SIMS data are achieved and both BED and TED phenomena are characterized. | |||
TO cite this article:Min Yu,Ru Huang,Xing Zhang. Atomistic Simulation on Ion Implantation and Annealing[OL].[12 December 2005] http://en.paper.edu.cn/en_releasepaper/content/4299 |
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