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1. A new high precision CMOS bandgap voltage reference | |||
HUANG Junkai,PAN Shaojun | |||
Electrics, Communication and Autocontrol Technology 14 March 2014 | |||
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Abstract:In bandgap references, the effect caused by the input offset of the operational amplifier can be effectively reduced by the utilization of cascade bipolar junction transistors (BJTs). But in modern CMOS logic processes, due to the base-emitter path of BJTs has a significant streaming effect on the collector current, which leads to a large temperature drift for the reference voltage. To solve this problem, a base-emitter current compensating technique is proposed in a cascade BJT bandgap reference structure to calibrate the curvature of the output voltage to temperature. The experiment results based on 0.18μm CMOS technology show that the temperature coefficient of reference voltage from -20℃ to 130℃ can reach 4.0 ppm/K. The layout area of this voltage reference is 130um×190um. | |||
TO cite this article:HUANG Junkai,PAN Shaojun. A new high precision CMOS bandgap voltage reference[OL].[14 March 2014] http://en.paper.edu.cn/en_releasepaper/content/4589041 |
2. Design of a CMOS Ultra-Wideband Distributed Amplifier | |||
Gao Wei,Zhong Shunan | |||
Electrics, Communication and Autocontrol Technology 18 February 2014 | |||
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Abstract:The high-speed data communication technology such as high-speed optical communication and ultra-wideband wireless communication, etc. demands a high-speed and broad-bandwidth integrated circuit exclusively used in communications. As an essential element in the integrated circuit, the amplifier is confined by its bandwidth and speed. The conventional amplifier is severely limited by the existence of parasitic capacitance. While the distributed amplifier is designed according to the distributed principle and transmission line theory, and overcomes the adverse the effects of parasitic capacitance to conventional amplifier, it becomes the optimal choice in modern high-speed communication integrated circuit for its extremely wide bandwidth and flat gain. This circuit has been designed under TSMC90nm RF CMOS process, it's a two stage cascaded amplifier, where each stage is composed by four gain cells. This design can achieve 18.0dB±1.0dB flat gain from 260M to 27.3GHz and its unity gain bandwidth is 32.5G, while consuming dc power of 78mW. This article focus on analyzing the relationship between number of stage and bandwidth, and noise optimize. | |||
TO cite this article:Gao Wei,Zhong Shunan. Design of a CMOS Ultra-Wideband Distributed Amplifier[OL].[18 February 2014] http://en.paper.edu.cn/en_releasepaper/content/4585397 |
3. Demagnification super-lens with graphene metamaterials for lithography | |||
Zhao Huijie,Han lihong,Yu Zhongyuan,Lin Benlong | |||
Electrics, Communication and Autocontrol Technology 16 January 2014 | |||
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Abstract:To achieve high resolution patterns at the imaging plane of super-lens, we developed a far-field optical lithography system. Firstly, the transformation optics method was employed for designing the demagnification super-lens system. Secondly, we proposed a novel nanolithography model with super-lens-photoresist-graphene layer structure to enhance the evanescent wave of electric field intensity distribution delivered by the transversal magnetic polarization wave. We use finite element method to analyze performance of the super-lens combining with multilayer structure and graphene back reflector. Numerical simulations indicate the lithographic resolution can reach to 50 nm, demonstrating the ability of nanolithography by this method. | |||
TO cite this article:Zhao Huijie,Han lihong,Yu Zhongyuan, et al. Demagnification super-lens with graphene metamaterials for lithography[OL].[16 January 2014] http://en.paper.edu.cn/en_releasepaper/content/4581869 |
4. Simulation of In2S3 /Cu(In,Ga)Se2 thin-film solar cells with the interfacial layer | |||
SUN Lin,HE Jun | |||
Electrics, Communication and Autocontrol Technology 23 December 2013 | |||
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Abstract:The performance of Cu(In,Ga)Se2 solar cells with In2S3 buffer layers and NaχCu1-χIn5S8 interfacial layers between buffer and absorber layers has been modeled and simulated using the AMPS-1D simulation software. The influences of the different band gap of In2S3 and the presence of NaχCu1-χIn5S8 on the device performance are investigated in detail. The results suggest that the suitable band gap of In2S3 should be in the range from 2.6 to 2.9 eV as opposed to 2.1e V for pure β-In2S3, and NaχCu1-χIn5S8 with high Cu contents lead to the significant deterioration of device performance. The responsible mechanisms for these results are also discussed. | |||
TO cite this article:SUN Lin,HE Jun. Simulation of In2S3 /Cu(In,Ga)Se2 thin-film solar cells with the interfacial layer[OL].[23 December 2013] http://en.paper.edu.cn/en_releasepaper/content/4574618 |
5. Simulation of Cu(In, Ga)Se2 solar cells with Zn1-χMgχO buffer layers by SCAPS-1D software | |||
SUN Lin,HE Jun | |||
Electrics, Communication and Autocontrol Technology 17 December 2013 | |||
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Abstract:The Zn1-χMgχO-buffer/Cu(In,Ga)Se2 solar cells with interface recombination are modeled using SCAPS-1D tool and the performances of these Cu(In,Ga)Se2 (CIGS) solar cells are simulated and analyzed systematically. Interface recombination is predominant in Zn1-χMgχO/CIGS solar cells with negative conduction band offset (CBO) and Zn1-χMgχO(Eg=3.6eV) is a very suitable buffer layer candidate for the CIGS(Eg=1.15eV) solar cells. Despite that the appropriate CBO between wide-bandgap CIGS absorber (Eg>1.3eV) and Zn1-χMgχO can be obtained by adding Mg content, the efficiency of wide-bandgap CIGS solar cells decreases gradually when the bandgap of Zn1-χMgχO increases from 3.6eV to 4.0eV gradually. This simulation result can be explained by the series resistance caused by the depletion layer in n-n heterojunction between ZnO window and Zn1-χMgχO buffer layer.????? | |||
TO cite this article:SUN Lin,HE Jun. Simulation of Cu(In, Ga)Se2 solar cells with Zn1-χMgχO buffer layers by SCAPS-1D software[OL].[17 December 2013] http://en.paper.edu.cn/en_releasepaper/content/4574612 |
6. An Interface Charge Model for Ferroelectric Field Effect Transistor | |||
XIAO Yongguang,TANG Minghua,LI Zheng | |||
Electrics, Communication and Autocontrol Technology 18 November 2013 | |||
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Abstract:An interface charge model for ferroelectric-gate field-effect transistor (FeFET) is developed by combining the basic device equations of metal-oxide-semiconductor field-effect transistors with the polarization characteristics of ferroelectric thin films. This model presents the characteristics of FeFET considering interface charge between the ferroelectric thin film and the insulator layer. Simulations demonstrate that the interface charge will cause the surface potential of the semiconductor and the drain current left shift, and the memory windows are narrowed down, which are resulted from the space charge of the surface of the semiconductor. Meanwhile, the value of polarization almost does not change in FeFET. Furthermore, the simulation of FeCMOS inverts indicates that the output voltage will left shift as the interface charge increases. | |||
TO cite this article:XIAO Yongguang,TANG Minghua,LI Zheng. An Interface Charge Model for Ferroelectric Field Effect Transistor[OL].[18 November 2013] http://en.paper.edu.cn/en_releasepaper/content/4570321 |
7. Combined Effects of Different Methods on Mitigating Charge Collection and Charge Sharing in 90 nm CMOS Process | |||
ZHANG Wanli,TANG Minghua,YAN Shaoan,MAO Yanhu | |||
Electrics, Communication and Autocontrol Technology 15 November 2013 | |||
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Abstract:A model of combining of guard rings and buried n+ layer in mitigating charge collection and charge sharing is presented in this paper. 3-D TCAD simulation results indicate that for 90-nm CMOS process, PMOS charge collection and charge sharing can be mitigated more effectively with the combination model than the solely use of guard rings or buried n+ layer. With the combination, a noticeable improvement on angled ion strikes is also represented. The model shows a significant advantage in high-energy ion strikes and angled ion strikes. | |||
TO cite this article:ZHANG Wanli,TANG Minghua,YAN Shaoan, et al. Combined Effects of Different Methods on Mitigating Charge Collection and Charge Sharing in 90 nm CMOS Process[OL].[15 November 2013] http://en.paper.edu.cn/en_releasepaper/content/4569928 |
8. Quasi-two-dimensional subthreshold voltage model for supra-deep-submicrometer MOSFET | |||
Shen Jing,Ke Daoming,Zhou Shaoyang,Xia Dan | |||
Electrics, Communication and Autocontrol Technology 26 February 2013 | |||
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Abstract:A new analytical quasi-two-dimensional surface potential model for short-channel MOSFET is presented in the paper. In this model, one-dimensional differential equation of the potential for the channel depletion layer can be derived by applying Gauss's law along the landscape of the channel depletion layer, the effect of the source and drain potential on the thickness of the channel depletion layer have been taken into account. The realationship between the potential and the thickness of the channel depletion layer can be obtained by solving the equation and the threshold voltage can be given by the thickness of the depletion layer we have obtained .we can verify the accuracy of this model by using the MEDICI software to simulate the MOSFET with different parameters, finally the results between simulation and calculations are in good agreement. | |||
TO cite this article:Shen Jing,Ke Daoming,Zhou Shaoyang, et al. Quasi-two-dimensional subthreshold voltage model for supra-deep-submicrometer MOSFET[OL].[26 February 2013] http://en.paper.edu.cn/en_releasepaper/content/4510954 |
9. A Switched-Capacitor Programmable-Gain Amplifier for High-Definition Video Analog Front-Ends | |||
ZHANG Hong,LI Xue,CHEN Yongliang,CHENG Jun | |||
Electrics, Communication and Autocontrol Technology 27 December 2012 | |||
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Abstract:A switched-capacitor programmable gain amplifier (PGA) for high-definition video analog front-ends (AFEs) is presented. The PGA also acts as the sample and holder of the ADC to reduce the power consumption and chip area of the whole AFE. The 9-bit gain and offset control DACs are embedded into the switched capacitor networks of the PGA. Simulated results show that the PGA achieves a gain range of 0.9 to 2.4V/V, and an offset control range of -230 to 230mV while consuming 10.1mA from a 1.8V power supply. An AFE based on the proposed PGA is fabricated in TSMC 0.18um process. Measurement results show that the AFE achieves the capability to process variant HDTV signals up to 1080p YPbPr and computer video signals up to UXGA (1600x1200 @75Hz). | |||
TO cite this article:ZHANG Hong,LI Xue,CHEN Yongliang, et al. A Switched-Capacitor Programmable-Gain Amplifier for High-Definition Video Analog Front-Ends[OL].[27 December 2012] http://en.paper.edu.cn/en_releasepaper/content/4505819 |
10. A Differential Voltage Reference Generator for Pipelined ADCs | |||
ZHANG Hong,WENG Xunwei,LI Xue,CHEN Yongliang,CHENG Jun | |||
Electrics, Communication and Autocontrol Technology 23 December 2012 | |||
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Abstract:A differential voltage reference generator for pipelined analog-to-digital converters (ADCs) is presented in this paper. A modified Brokaw bandgap reference (BGR) is adopted to generate an adjustable sub-1V reference voltage. A new single-ended to differential converter based on current conversion is proposed to obtain the required differential voltage reference from the output of BGR directly. Fabricated in TSMC 0.18 um CMOS technology, the proposed circuit generates a 0.5-V differential reference voltage with a temperature coefficient of less than 46 ppm/ oC. The power consumption is 3.5 mW under a 1.8-V power supply. ????? | |||
TO cite this article:ZHANG Hong,WENG Xunwei,LI Xue, et al. A Differential Voltage Reference Generator for Pipelined ADCs[OL].[23 December 2012] http://en.paper.edu.cn/en_releasepaper/content/4505924 |
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