Abstract:Two dimensional transition metal chalcogenides have important application prospects in optoelectronic devices, energy storage, catalysis and other fields due to their excellent properties. The research on this material covers its electronic properties, optical properties and so on, but the related research on transport properties is less. The electronic properties and applications of materials largely depend on their crystal structures. In this project, the first principles density functional theory and non-equilibrium Green\'s function are used to calculate the quantum transport of NbSeTe- MoSeTe- NbSeTe transport structure, and we study its electronic transport properties. By applying bias voltage to the electrode, the difference of transmission coefficient under different bias voltage and the relationship between current and bias voltage are discussed. By the means of analyzing the transmission spectrum of the non-equilibrium state of the device, we can understand the quantum transport properties of non-equilibrium state. When the bias voltage is less than 60mV, the transmission coefficient spectrum has no obvious change; while in 80mV or 100mV, it becomes larger having a positive effect on the current.

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	1. First-principle Study on Transport Properties of 2D Janus NbSeTe-MoSeTe-NbSeTe Lateral Heterostructure
	ZHENG Yanan,YE Han
	Electrics, Communication and Autocontrol Technology 11 March 2021
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	Abstract:Two dimensional transition metal chalcogenides have important application prospects in optoelectronic devices, energy storage, catalysis and other fields due to their excellent properties. The research on this material covers its electronic properties, optical properties and so on, but the related research on transport properties is less. The electronic properties and applications of materials largely depend on their crystal structures. In this project, the first principles density functional theory and non-equilibrium Green\'s function are used to calculate the quantum transport of NbSeTe- MoSeTe- NbSeTe transport structure, and we study its electronic transport properties. By applying bias voltage to the electrode, the difference of transmission coefficient under different bias voltage and the relationship between current and bias voltage are discussed. By the means of analyzing the transmission spectrum of the non-equilibrium state of the device, we can understand the quantum transport properties of non-equilibrium state. When the bias voltage is less than 60mV, the transmission coefficient spectrum has no obvious change; while in 80mV or 100mV, it becomes larger having a positive effect on the current.
	TO cite this article:ZHENG Yanan,YE Han. First-principle Study on Transport Properties of 2D Janus NbSeTe-MoSeTe-NbSeTe Lateral Heterostructure[OL].[11 March 2021] http://en.paper.edu.cn/en_releasepaper/content/4754044


	2. More accurate estimation of the linewidth of energy level dispersion in GaAs based Semiconductor Heterostructures
	KONG Xinyu,REN Xiaomin,LIU Hao,WANG Qi,LIU Kai,HUANG Yongqing
	Electrics, Communication and Autocontrol Technology 03 April 2020
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	Abstract:As a new advancement of the theory of fractional dimensionality of electron states architecture in semiconductor heterostructure physics, more accurate estimation of the linewidth of energy level dispersion in GaAs based semiconductor heterostructures at a temperature of 300K has been made by adopting a modified energy level dispersion function featuring an asymmetric lineshape and the relevant dimensional similarity functions modified mainly by introducing a novel concept of quantization baseline of density of states. It is determined as about 0.00221eV, which is in the same order of magnitude with the previous result, but about 10% larger than that. This work may magnify the impact of the fractional dimensionality theory on the development of semiconductor quantum electronics and optoelectronics and even that of fundamental physics.
	TO cite this article:KONG Xinyu,REN Xiaomin,LIU Hao, et al. More accurate estimation of the linewidth of energy level dispersion in GaAs based Semiconductor Heterostructures[OL].[ 3 April 2020] http://en.paper.edu.cn/en_releasepaper/content/4751465

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	3. A simplified layer-by-layer transfer process towards high-quality multilayer graphene electrode fabrication
	Dong Wang?,,1,Jing Ning1,Qin Lu1,Meishan Mu1,Yue Hao1,Jincheng Zhang1,
	Electrics, Communication and Autocontrol Technology 08 December 2015
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	Abstract:In this paper we present a high-quality multilayer graphene electrode fabrication using a simplified layer-by-layer transfer progress.we use highly purified methane as carbon source at 1030℃ to synthesis high-quality monolayer graphene by chemical vapor deposition. The coverage of monolayer graphene is more than 90% and carrier mobility is much higher than 300cm2/Vs with the transparent of 97%.during the transfer process,we use simplified layer-by-layer transfer technology to fabricate high-quality multi-layer(4~5) graphene transparent conductive film and the optical tansmittance of 5 layer graphene tansparent conductive film is high than 87.5%(550nm).The excellent surface and roughness is indicate by AFM and SEM.To further demonstrate availability of 5-layer graphene tranparent conductive,we use electon beam evaporation to prepare high-property solar cells based on P3HT:PCBM transport layer and graphene/MoO3.The analysis of current-voltage characteristic indicates that graphene transparent conductive film obviously improve the solar cells' electical conductivty.
	TO cite this article:Dong Wang?,*,1,Jing Ning1,Qin Lu1, et al. A simplified layer-by-layer transfer process towards high-quality multilayer graphene electrode fabrication[OL].[ 8 December 2015] http://en.paper.edu.cn/en_releasepaper/content/4669079


	4. A Bottleneck-based dynamic scheduling algorithm for semiconductor wafer fabrication
	Cao Zhengcai,Deng Jijie
	Electrics, Communication and Autocontrol Technology 21 February 2013
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	Abstract:Semiconductor wafer fabrication is a very complicated manufacturing system with characteristics such as reentry of lots into machines, alternative machine with unequal capacity and shifting bottlenecks. The optimization and scheduling of semiconductor wafer fabrication has long been a hot research field. Bottleneck is the key factor to the wafer fabrication which has essential influence on the throughput rate, cycle time, time-delivery rate, etc. The scheduling policies on bottleneck machines have significant impact on cost decreasing, achieving throughput target and improving production-resource scheduling and therefore need to be optimized. In this paper, considering the characteristic information concerning bottleneck and whole production line, a rolling horizon bottleneck prediction method is proposed through predict the wait time of the lot in machines and the machine load. Then, based on the above prediction bottleneck, we proposed a novel rolling horizon dynamic bottleneck-based scheduling algorithm. The algorithm analyzes the key factors which influence the bottleneck shifting and the upstream and downstream scheduling policies of bottleneck. Applied to a simulation wafer fabrication, our proposed bottleneck prediction method and bottleneck-based scheduling algorithm improve the cycle time, machine utility apparently compared to other heuristic scheduling method
	TO cite this article:Cao Zhengcai,Deng Jijie. A Bottleneck-based dynamic scheduling algorithm for semiconductor wafer fabrication[OL].[21 February 2013] http://en.paper.edu.cn/en_releasepaper/content/4522240


	5. A Low-Sensitivity Negative Resistance Load Fully Differential OTA under Low Voltage 40nm CMOS Logic Process
	Ning Ning,Fan Yang,Sui Zhiling,Luo Rui,Wu Shuangyi
	Electrics, Communication and Autocontrol Technology 16 March 2012
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	Abstract:A low-sensitivity negative resistance load fully differential operational transconductance amplifier （OTA） with low supply voltage is proposed under standard 40nm logic CMOS process. By using optimized low-sensitivity negative resistance load, the gain immunity towards process variation is effectively improved. Simulated with 40nm logic process model and 1.1V power supply, the results show that the OTA obtained a gain enhancement of 23.85dB and the gain variations is greatly limited.
	TO cite this article:Ning Ning,Fan Yang,Sui Zhiling, et al. A Low-Sensitivity Negative Resistance Load Fully Differential OTA under Low Voltage 40nm CMOS Logic Process[OL].[16 March 2012] http://en.paper.edu.cn/en_releasepaper/content/4471927


	6. Efficient Reliability Dispositioning of Gross Fail Area Defects
	Sun Yanlong,Rong Guoguang
	Electrics, Communication and Autocontrol Technology 11 August 2011
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	Abstract:Various issues in semiconductor manufacturing such as equipment malfunction or process marginalities can result in specific spatial failure patterns of devices at wafer Sort, which could lead to yield or reliability issues in assembly test or with the end customer. Due to the variability and complexity of these Gross Fail Area (GFA) defects, it is difficult, and in some cases nearly impossible to automate the containment and dispositioning of wafers without severely affecting factory output. Containment of impacted material using traditional Statistical Bin Limits (SBL) and limited GFA detection screens post Sort, can often put too much material on hold, or worse, allow impacted material to escape the factory. The current dispositioning procedures are mostly manual and tedious, requiring the review by engineers of large quantities of both affected and unaffected material. The manual procedures, prone to user error, may involve risk of RSI (repetitious stress injury) from the large extent of 'click and kill' inking. In this paper we describe a new breakthrough methodology for automating the accurate screening and inking of certain GFA defects. The wafer map of the Sort bin test results is first converted into a pixel image with just the failed bins that constitute the GFA of interest. Image analysis techniques are applied to identify and extract attributes such as location, size, orientation etc. of the clusters of contiguous failed dice. These attributes are used in rules that are implemented in software to test for the existence of the specific failure patterns, resulting in highly accurate screening. Good die, known to have impaired functionality due to their being adjacent to the clusters meeting specific fail criteria, are then inked programmatically, as their location on the wafer and other descriptive information are known. The entire process is automated, requiring no human intervention.
	TO cite this article:Sun Yanlong,Rong Guoguang. Efficient Reliability Dispositioning of Gross Fail Area Defects[OL].[11 August 2011] http://en.paper.edu.cn/en_releasepaper/content/4438057


	7. Modular Fault Diagnosis for the Closed-Loop Operational Amplifier Based Analog Circuits
	Hu Mei,Wang Hong,Yang Shiyuan
	Electrics, Communication and Autocontrol Technology 05 September 2008
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	Abstract:This paper describes a dictionary method based on slope fault feature for hard and soft faults diagnosis of modular analog circuit. In complicated circuit when the closed-loop operational amplifier (CLOA) is used as a basic building block, the circuit can be divided into several modules based on the CLOA, and then extract the unified slope fault feature of each module to establish fault dictionary, which can diagnose hard and soft faults of all the components and the OA of the corresponding module. Finally, experiments are demonstrated to validate the efficiency of the proposed approach: the coverage of hard and soft faults of OA is 64.4% and 86.4% respectively, and the fault coverage of passive components is 100%.
	TO cite this article:Hu Mei,Wang Hong,Yang Shiyuan. Modular Fault Diagnosis for the Closed-Loop Operational Amplifier Based Analog Circuits[OL].[ 5 September 2008] http://en.paper.edu.cn/en_releasepaper/content/23814


	8. Physics-based Modeling for Si CMOS On-Chip Spiral Inductors using Characteristic functions
	Wu Zhongjie,Yu Tian,Yufeng Zhu,Nan Jiang,Yusong Chi,Huang Fengyi
	Electrics, Communication and Autocontrol Technology 14 April 2008
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	Abstract:We present an extended review on the modeling of silicon CMOS on-chip spiral inductors based on S-parameter measurement. A series of equivalent circuits including different number of n-π structure with both symmetric and asymmetric geometries have been studied. The parameter extraction is carried out using a set of characteristic functions derived from the equivalent circuit without iterative optimization. As verified by a series of inductors fabricated with a 0.18 μm CMOS process, a good agreement between the measured and simulated data over a wide frequency range has been obtained. The characteristic-function approach can alleviate the potential problem of multiple solutions pertaining to conventional numerical method based on iteration optimization.
	TO cite this article:Wu Zhongjie,Yu Tian,Yufeng Zhu, et al. Physics-based Modeling for Si CMOS On-Chip Spiral Inductors using Characteristic functions[OL].[14 April 2008] http://en.paper.edu.cn/en_releasepaper/content/20462

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